The present invention disclosed herein relates to a non-volatile semiconductor device, and more particularly, to a memory cell array of a flash memory.
Recently, demands for increasing a capacity of an erase sector (hereinafter, referred to as a sector) have been increased. Although typical sector capacity is 0.5 Mbits, products having a sector capacity of 2 Mbits are developed and extensively used. This is because a multi-level cell (MLC) is applied to a semiconductor device and its chip size is miniaturized.
If a memory having the same capacity as the MLC is realized with a single-level cell (SLC) technique, there are diverse methods as follows.
First, a method is provided for multiplying the typical number of bit lines in a memory cell array by four times.
Second, a method is provided for multiplying the typical number of word lines in a memory cell array by four times.
Third, a method is provided for multiplying the typical number of bit lines and the typical number of word lines in a memory cell array by two times, respectively.
Fourth, a method is provided for using four typical sectors to resemble one sector.
FIGS. 3 through 6 are plan views illustrating one to fourth methods. FIG. 3 illustrates a plan view when the first method is used. Compared to a memory cell array of 0.5 Mbits of FIG. 2 including 512 word lines and 1024 bit lines in a P well region 11, the memory cell array of FIG. 3 includes 4096 bit lines which are four times of the 1024 bit lines of FIG. 2. Additionally, FIG. 4 illustrates a plan view when the second method is used. Compared to the memory cell array of FIG. 2, the memory cell array of FIG. 4 includes 2048 word lines which are four times of the 512 word lines of FIG. 2. FIG. 5 illustrates a plan view when the third method is used. Compared to the memory cell array of FIG. 2, the memory cell array of FIG. 5 includes 1024 word lines and 2048 bit lines, which are two times of the 512 word lines and the 1024 bit lines of FIG. 2, respectively. FIG. 6 illustrates a view when the fourth method is used. The memory cell array of FIG. 6 uses four memory cell arrays (i.e., four sectors) of FIG. 2 as one memory cell array (i.e., one sector). The techniques related to the above methods are disclosed in Japanese Patent No. 3570879.
However, if the above methods are used, there are several difficulties as follows.
In a first case, if the length of a word line is four times that of a typical word line, even if word line drivers are disposed at both ends of a word line and driven, a time needed for a word line to reach a predetermined time is two times that of a typical method. Therefore, it is difficult to make a reading speed fast and thus it may become slower.
In a second case, if the length of a bit line is four times that of a typical bit line, it may affect a reading speed. Additionally, during an input operation of a memory cell, because of a bit line resistance, an actual voltage applied to a drain of a memory cell is lowered, and input characteristics in a sector are deteriorated. Additionally, the number of memory cells connected to a bit line is four times that of typical memory cells. Accordingly, when considering a cycling characteristics of a sector, drain disturb in a memory cell becomes four times typical drain disturb, and thus, it may be hard to obtain reliability.
In a third case, even though it is less disadvantageous than the first and second cases, the same limitations occur. In an aspect of a word line, time increase may be allowable or word line drivers may be disposed at both ends of the word line in order to be identical to the typical word line. However, in an aspect of cycling, drain disturb still remains.
In a fourth case, although characteristics are the same as typical characteristics, an area between sectors is needed more in terms of a layout. Therefore, this situation is unfavorable.